PIC16F1825-E/ML【PDF 16/208 页】MCU PIC 14K FLASH 1K RAM 16QFN

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137

ATmega8515(L)

2512K–AVR–01/10

AVR USART vs. AVR UART –

Compatibility

The USART is fully compatible with the AVR UART regarding:

Bit locations inside all USART Registers

Baud Rate Generation

Transmitter Operation

Transmit Buffer Functionality

Receiver Operation

However, the receive buffering has two improvements that will affect the compatibility in

some special cases:

A second Buffer Register has been added. The two Buffer Registers operate as a

circular FIFO buffer. Therefore the UDR must only be read once for each incoming

data. More important is the fact that the Error Flags (FE and DOR) and the ninth

data bit (RXB8) are buffered with the data in the receive buffer. Therefore the status

bits must always be read before the UDR Register is read. Otherwise the error

status will be lost since the buffer state is lost.

The Receiver Shift Register can now act as a third buffer level. This is done by

allowing the received data to remain in the serial Shift Register (see Figure 64) if the

Buffer Registers are full, until a new start bit is detected. The USART is therefore

more resistant to Data OverRun (DOR) error conditions.

The following control bits have changed name, but have same functionality and register

location:

CHR9 is changed to UCSZ2

OR is changed to DOR

Clock Generation

The clock generation logic generates the base clock for the Transmitter and Receiver.

The USART supports four modes of clock operation: Normal asynchronous, Double

Speed asynchronous, Master synchronous and Slave synchronous mode. The UMSEL

bit in USART Control and Status Register C (UCSRC) selects between asynchronous

and synchronous operation. Double Speed (asynchronous mode only) is controlled by

the U2X found in the UCSRA Register. When using Synchronous mode (UMSEL = 1),

the Data Direction Register for the XCK pin (DDR_XCK) controls whether the clock

source is internal (Master mode) or external (Slave mode). The XCK pin is only active

when using Synchronous mode.

Figure 65 shows a block diagram of the clock generation logic.

Figure 65. Clock Generation Logic, Block Diagram

Prescaling

Down-counter

UBRR

fosc

UBRR+1

Sync

OSC

XCK

txclk

U2X

UMSEL

DDR_XCK

xcki

xcko

DDR_XCK

rxclk

Edge

Detector

UCPOL

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